FPGA Acceleration of SP1 with AntChain OpenLabs

We’re excited to announce the development of FPGA acceleration for SP1 in collaboration with AntChain OpenLabs. AntChain, a subsidiary of Ant Digital Technologies (incubated from Ant Group) and an affiliate of Chinese multi-national Ant Group and Alibaba Group, has managed to improve SP1’s performance by 20x v.s. CPUs with their FPGA implementation. They will be providing FPGA accelerated SP1 proving on the Succinct Prover Network.

Historically, SP1 has been accelerated using general-purpose hardware like CPUs and GPUs. While we’ve seen strong performance on these platforms, we believe a new trajectory is possible by investing in custom silicon. Benchmarks on the AMD Alveo U55C FPGA show that an early research preview of this accelerator is already 15-20× faster than CPU, demonstrating the massive potential of specialized hardware. FPGAs serve as an ideal stepping stone toward ASICs, allowing us to validate and iterate on custom designs before committing to silicon.

This makes SP1 the first production-ready RISC-V zkVM with end-to-end FPGA hardware acceleration, a commitment that positions us ahead of the competition. Even more exciting, Zan (the hardware team behind the FPGA work) will be joining the Succinct Prover Network, bringing continuously improving performance directly into the SP1 ecosystem. It’s a clear demonstration of the Prover Network’s ability to coordinate incentives for external hardware teams to accelerate SP1 and directly benefit from doing so. 

Behind the scenes, the FPGA accelerator is powered by Zetta, an FPGA architecture developed specifically for SP1. Zetta is implemented on the AMD Alveo U55C and is designed to accelerate SP1’s proof generation pipeline with custom modules for CosetNTT operations, Merkle tree generation, and vectorized computations like permutation trace generation and FRI folding. Its modular design connects to high-bandwidth memory (HBM) via a CrossBar and Data Bus for efficient parallel data movement, and interfaces with the host via PCIe. By supporting programmable instruction sequences, Zetta can also flexibly accelerate any set of circuits inside SP1, including those yet to be developed.

AntChain OpenLabs benchmarked Zetta against the CPU implementation of SP1 v4.1.0, focusing on end-to-end performance of the Core Prover and Compress Prover. The table below highlights the performance gains across a range of programs from the zkvm-perf benchmark suite.

We’re excited to continue collaborating with AntChain OpenLabs on the development of the FPGA accelerator and are optimistic that this work will lead to substantial reductions in proving costs for our customers. You can learn more about Zetta’s architecture and benchmarks in their blog post.

At Succinct, we’re committed to pushing the boundaries of what’s possible with SP1, not just in terms of security and developer experience, but also raw performance. The FPGA accelerator is just one part of a broader roadmap aimed at redefining the speed and scalability of zero-knowledge proving. Stay tuned for more, including our recent work on SP1 Hypercube and breakthroughs in real-time proving, as we continue to expand the frontier of what SP1 can do.